Integrated circuits are routinely tested to insure that they are functioning properly before a product containing the integrated circuit is shipped, sold, or placed into use. The time required for testing can vary from seconds to several minutes depending upon the particular integrated circuit, its complexity, and its function. Typically, test pattern data created for such testing purposes is often quite large and difficult to manage.
Various approaches have been taken in the art to better manage the large test pattern data required for testing integrated circuits. One solution has been to specify test pattern data for all signals on every cycle in a flat tabular format. Signals are associated with unique identifiers in columns. Cycles are associated with unique identifiers in rows. This format requires a large amount of storage space (the number of signals multiplied by the number of cycles). Applying standard compression software can reduce the size significantly, but this depends upon the data. Another disadvantage with this method is that it is difficult to see which signals are changing.
Another approach has been to specify the test pattern data only when the signal names and their associated values change. For each cycle, there are signal names having associated values. In the next cycle, only those signals and associated values that are different from the previous cycle are specified. This approach has great utility because signals in test pattern data for integrated circuits tend not to change much between cycles. However, this format takes more time to process, as the signal names must be processed each time the data changes. Additionally, though this format is typically smaller than a flat format, it does not compress as well.
An approach taken by Texas Instruments for testing high complexity circuits employs a test description language which has special statements which simplify the description of test vectors for scan-testable circuits. The goal is to eliminate redundant information by only having to describe non-redundant information.
This approach, described in a test development engineering note, published in October 1992, describes allowing test pattern data to specify a vector string which can have a multitude of characters. One such character is a space character, which is used to signify that a pin in a current cycle has the most recently applied signal from the previous cycle. The use of this space character can reduce the repetitiveness of data being entered, however, because the test pattern data is intermixed with all other specification data in the file, the use of the space character does not significantly improve the compressibility of the file. Also, because of the intermix of test pattern data and commands, the test pattern data contained in the file described by Texas Instruments is not capable of being processed sequentially, line by line, to automatically process an existing file of test pattern data to create a more compressible file. Thus, the Texas Instrument approach is not designed for improving compressibility of test pattern data.
It is thus apparent that there is a need in the art for a better way to manage large amounts of test pattern data for testing integrated circuits. There is also a need in the art to more efficiently reduce the amount of storage space required for large amounts of test pattern data. There is further a need in the art for a better way to represent the test pattern data so that it will compress more efficiently than the current art. There is also a need in the art to store in a separate file header and other information so that only test pattern data itself is stored in the test pattern data file. The present invention meets these and other needs in the art.